Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design.This role is based in Noida. But you'll also get to visit other locations in India and globe, so you'll need to go where this job takes you. In return, you'll get the chance to work with teams impacting entire cities, countries, and the shape of things to come.Responsibilities for this role include: Working on the physical design execution from C-based digital implementation and the power estimation/optimization Conducting complex analyses and debug of results using statistics and data predictions to identify issues or areas for improvement. Work with customers, research partners and academia to drive future innovation-related initiatives including the development of new scripts and flows. Leverage infrastructure and learning developed from such initiatives to products in Siemens EDA Analyze and improve PPA for HLS-generated RTL by improving Flows and Methodologies. Participate in the specification, architecture, design, and development of features. Be a force for improving development processes and product quality. Work effectively with globally distributed engineering teams. Experience and Qualifications: Graduate or Postgraduate in Computer Science and Electrical/Electronics Engineering, Minimum 2-4 years' experience in Design/EDA Industry. We need someone with knowledge of entire flow from RTL to GDS (Logic Synthesis, Floor planning, Power planning, Placement/CTS/Routing and corresponding optimization steps, Timing Analysis). Good knowledge of digital electrical circuits. Also, ability to pickup new flows, learn on the job and influence QOR is a must; Are you someone with previous experience and knowledge of tools for "Physical Design Implementation" in advanced technologies nodes! Understanding of power analysis and power integrity analysis. Must demonstrate excellent analytical and problem-solving capabilities, and strong communication skills. Scripting skills in Tcl & Python are required to be able to develop/support flows. Desirable We are looking for an individual with previous experience with High Level Synthesis e.g. Catapult. Solid understanding of one or more HDL language and/or SystemC. Programming skills in C and C++, Tcl or Python, preferably on Linux platform. Worked on 3DIC designs or flow/methodology development. Communication Proficiency in English with strong interpersonal and excellent oral and written communication skills. Ability to collaborate as part of globally distributed team. Also, Self-motivated and able to work independently. Good communication skills and ability & desire to work in a multi-functional team environment. We are SiemensA collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow!We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home.We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.#LI-EDA#LI-HYBRIDTransform the everyday and Accelerate transformation.Salary: . Date posted: 03/28/2024 09:14 PM

Principal PD Engineer

Microsoft Games, Multiple Locations, Any

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Hardware, Infrastructure Management, and Fundamentals Engineering (HIFE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.ResponsibilitiesIn this high impact role on the team, you will be responsible to: Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification. Own complete PD execution of Sub-systems/Sub-chips instantiating/integrating multiple other Physical partitions. Own partition floorplanning for optimizing blocks for Power, Performance and Area. Collaborate and influence various aspects of PD Methodology will also be key. Have close collaboration with RTL team (RTL2PD liaison) to help drive and resolve design issues related to block closure. Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach. Implement robust clock distribution solutions using appropriate methods that meet design requirements. Make good independent technical trade-offs between power, area, and timing (PPA). Be able to guide and coordinate with all sub-partitions PD to be able to take the Sub-chip through PD (construction through signoff) closure. Additionally influence key pieces of PD implementation methodology or specific areas such as Clocking. Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues upfront and ensure those are fixed in the next PD TFM release from CAD or are updated in the design project layer (as appropriate). Mentor junior engineers on technical issues. Be fully hands-on in your individual ownerships as individual contributor and collaborate cross-team on aspects of SC/SS execution, integration & delivery. Qualifications BS/MS in Electrical or Computer Engineering Min 15+ years of experience in semiconductor design. Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams. Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification. Preferred: Large SoC/CPU/IP design tape-out experience in the latest foundry process nodes. Led PD teams to deliver multiple PD partitions integrated in a subchip/subsystem, having excellent project management skills and ability to juggle multiple projects at once. Strong understanding of constraints generation, STA, timing optimization, and timing closure. In-depth understanding of design tradeoffs for power, performance, and area. Hands on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs. Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, Fusion Compiler, Innovus etc. Experience and knowledge of formal equivalency checks, LEC, LP, UPF, reliability, SI, and Noise. Experience in driving/contributing/influencing PD Methodology will be required. Overall know how of PD-TFM, exposure and some hands-on experience with PD flows bring up/setup/flow flush and PD methodology will be a bonus. Strong problem-solving and data analysis skills. Automation skills using scripting languages such as Perl, TCL, or Python. Technically leading/guiding a team of multiple PD engineers in order to deliver a Sub-Chip/SoC will be a big plus. Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form . Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.Salary: . Date posted: 04/03/2024 03:17 AM

Global FICC Transformation - Program/Project Manager - Vice President

JPMorgan Chase, Mumbai, Any

You are a strategic thinker passionate about driving solutions in "Project/ Program management". You have found the right teamAs a Project/Program Manager within our Digital & Platform Services Market Operations Transformation team, you will be tasked with defining, refining, and achieving the set objectives for our firm. Your responsibilities will include overseeing the delivery of Strategic End State Programs that aim to scale, reduce risk, and enhance the overall client experience. You will be leading governance routines, managing work streams and projects across Market Operations. This role necessitates collaboration with various internal teams and business leaders to deliver Target State Solutions that align with our strategy, cost optimization, regulatory reporting, and end state client experience.As a Project Manager for Markets Operations Cross-LOB Initiatives, you'll manage strategic and tactical projects, and provide analytical, reporting, communications, and change management support for Markets Operations senior management. Projects may include digitization/automation, operational efficiency, regulatory, control, business resiliency and/or people initiatives. Job Responsibilities: Lead, manage, and drive execution of key programs across multiple Markets Operations areas. Support the governance infrastructure and protocols of the program. Manage end-to-end delivery of projects/programs, partnering closely with teams across Operations, Technology, Sales & Trading, Data & Analytics, Legal & Compliance, Finance, Human Resources, and other corporate functions. This will include project planning and analysis, resource management, driving or overseeing project execution, and reporting of status to senior management. Conduct data collection, data analysis, and synthesis to develop recommendations for management or to inform management decisions. Leverage the latest digital tools and technologies to support development of scalable, leading-edge solutions. Provide reporting, analytical, communications and project support to senior Markets Operations management Design and documentation of organizational and operational processes to support program execution. Partner within the business and senior-level stakeholders to achieve stated goals. Lead problem solving and data driven decision making inclusive of process design, re-engineering, and target state modeling.Required qualifications, capabilities and skills Bachelor's degree required. Minimum10years project management / business analysis experience Markets or other related financial services experience is must; experience in an operations and knowledge of industry regulations Excellent written/verbal communication and presentations skills targeting various stakeholders and senior management. Intermediate/Advanced experience using Microsoft Office, including Excel, and PowerPoint Excellent analytical and logical thinking to understand and analyze complex business problems. Strong data analysis skills, including analysis of operational, process, and financial data. Strong organizational and prioritization skills, detail-oriented, and strong interpersonal and influencing skills. End-to-end project management experience, including scoping, business case development, implementation, results measurement and change management. Ability to analyze and resolve project-related issues and follow through with set objectives. Experience with emerging technologies and the latest digital tools About usJ.P. Morgan is a global leader in financial services, providing strategic advice and products to the world's most prominent corporations, governments, wealthy individuals and institutional investors. Our first-class business in a first-class way approach to serving clients drives everything we do. We strive to build trusted, long-term partnerships to help our clients achieve their business objectives.We recognize that our people are our strength and the diverse talents they bring to our global workforce are directly linked to our success. We are an equal opportunity employer and place a high value on diversity and inclusion at our company. We do not discriminate on the basis of any protected attribute, including race, religion, color, national origin, gender, sexual orientation, gender identity, gender expression, age, marital or veteran status, pregnancy or disability, or any other basis protected under applicable law. We also make reasonable accommodations for applicants' and employees' religious practices and beliefs, as well as mental health or physical disability needs. Visit our FAQs for more information about requesting an accommodation.About the TeamThe Corporate & Investment Bank is a global leader across investment banking, wholesale payments, markets and securities services. The world's most important corporations, governments and institutions entrust us with their business in more than 100 countries. We provide strategic advice, raise capital, manage risk and extend liquidity in markets around the world.Salary: . Date posted: 04/05/2024 10:24 PM

Business Intelligence Engineer, Amazon Appstore

Amazon, Bengaluru, KA, IN

DESCRIPTIONAmazon Appstore is a fast-growing Organization and responsible for providing delightful customer experiences across Amazon devices (FireTV, Tablets) with a vast selection of relevant apps, games, and services. The Appstore team is seeking an experienced Business Intelligence Engineer to join our central Data Engineering and Analytics team. The role will be responsible for closely partnering with Data Engineers, Software Development Engineers to build data transformations and provide actionable insights for our Product and Tech stakeholders. This is an exciting opportunity to work on very large datasets and influence products that impact tens of millions of customers on a daily basis.Key job responsibilitiesIn this role, you will:- Analyze and extract relevant information from large, complicated data sets of structured and unstructured data to identify insights to influence product roadmap.- Design, develop and maintain scaled, automated, user-friendly systems, reports, dashboards, etc. that will support business teams.- Collaborate with product and technical teams to develop and track KPIs, automated reporting/process solutions and data infrastructure improvements to meet product team needs.- Serve as liaison between the product and technical teams to provide actionable insights and drive deep dive investigations into future improvements.- Drive data gathering and manipulation, synthesis and modeling, problem solving, and communication of insights and recommendations.We are open to hiring candidates to work out of one of the following locations:Bangalore, KA, IND | Bengaluru, KA, INDBASIC QUALIFICATIONS- Bachelor's degree in Computer Science, Engineering, Math, Finance, or related discipline- 2+ years of professional experience working with large data sets and writing complex SQL queries to analyze data- Experience with data modeling, data warehousing, and building ETL pipelines- Experience using business intelligence reporting tools (Excel, Tableau, Business Objects, Cognos etc.) and AWS big data technologies (Redshift, EMR, S3 etc.)- Ability to display complex quantitative data in a simple, intuitive format and to present findings in a clear and concise mannerPREFERRED QUALIFICATIONS- Outstanding quantitative modeling and statistical analysis skills- Advanced ability to draw insights from data and clearly communicate them (verbal/written) to the stakeholders and senior management as required- Advanced knowledge and expertise with Data modeling skills, Advanced SQL with Redshift, Oracle, MySQL, and Columnar Databases.- Design and scripting experience in one of Python, Perl, Shell script

Lead ASIC-FPGA Verification Engineer

Boeing, Bangalore, Any

Job DescriptionAt Boeing, we innovate and collaborate to make the world a better place. From the seabed to outer space, you can contribute to work that matters with a company where diversity, equity and inclusion are shared values. We're committed to fostering an environment for every teammate that's welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us.Boeing is the world's largest (Per Boeing LinkedIn page) aerospace company and a leading provider of commercial airplanes, defense, space, and security systems, and global services. Building on a legacy of over a century of innovation and leadership, Boeing continues to lead the way in technology and innovation, customer delivery, and investment in its people and future growth of aerospace.In India, Boeing has been a strong partner to the Indian aerospace and defense sectors for more than 75 years. People at Boeing have been supporting mission readiness and modernization of India's defense forces, and enabling connected, safer, and smarter flying experiences, in the sky, in the seas, and in space.Technology for today and tomorrowThe Boeing India Engineering & Technology Center (BIETC) is a 3000+ diverse engineering workforce that contributes to global aerospace growth. Our engineers deliver cutting-edge R&D, innovation, and high-quality engineering work in global markets, and leverage new-age technologies such as AI/ML, IoT, Cloud, Model-Based Engineering, and Additive Manufacturing, shaping the future of aerospace.People-driven cultureAt Boeing, we believe creativity and innovation thrives when every employee is trusted, empowered, and has the flexibility to choose, grow, learn, and explore. We offer variable arrangements depending upon business and customer needs, and professional pursuits that offer greater flexibility in the way our people work. We also believe that collaboration, frequent team engagements, and face-to-face meetings bring diverse perspectives and thoughts - enabling every voice to be heard and every perspective to be respected. No matter where or how our teammates work, we are committed to positively shaping people's careers and being thoughtful about employee wellbeing.At Boeing, we are inclusive, diverse, and transformative. With us, you can create and contribute to what matters most in your career, community, country, and world. Join us in powering the progress of global aerospace. Position Overview Boeing India Engineering seeks a Lead ASIC-FPGA Verification Engineer with considerable experience in design to support multiple product lines in commercial and defense electronics development. Primary Responsibilities: Use high-level architectural documentation along with algorithm description and implement functions for test bench architecture and designDevelop models in System Verilog to verify design implementation and develop and run scripts and MakefilesLeads analysis of customer and system requirements and development of architectural approaches and detailed specifications for various electronic productsLeads reviews of testing and analysis activity to assure compliance to requirementsIdentifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirementsLeads activities in support of functional verification, simulation, emulation, safety and other technical services/methodologiesProficient in crafting verification plan IPs/SubsystemsCoordinates engineering support throughout the lifecycle of the product.Plans research projects to develop concepts for future product designs to meet projected requirementsWorks under minimal directionShould Have exposure to SOI3 Audits and also have DO-254 Certification or training Basic Qualifications (Required Skills/Experience): Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry is required14 to 16 years of experience in Digital ASIC/FPGA verification.4 or more years of concurrent exposure to Digital ASIC/FPGA Design. Preferred Qualifications (Desired Skills/Experience): Experience leading development of architectural approaches from customer and system requirements.Experience identifying, tracking, and providing status of technical performance metrics to measure progress and ensure compliance with requirements.Experience directing a team of engineers for technical excellence.Experience developing and leading sophisticated and high data rate design verification bench.Expert in writing Universal Verification Methodology (UVM) sequences and virtual sequences and its concepts like Inheritance, Polymorphism, etc.Expert in using Universal Verification Methodology (UVM): Experience crafting drivers, monitors, predictors, and scoreboards.Work experience crafting a self-checking simulation test bench from scratch for SoCs/ASIC/FPGA.Work experience performing clock cross domain analysis (CDC).Expertise in verification working with internal/external VIPs, its development and evaluation with multiple vendors.In-hand depth upon System VerilogWork experience using Linux or Unix terminal commands.Experience using scripting languages: Make, Perl, Python, shell scripts, etc.Experience using Revision Control Systems: Subversion (SVN), CVS, Git.Good Understanding upon designing digital ASIC/FPGA architectural design documents (micro-architecture documents with timing diagrams, detailed design blocks, etc.).Good Understanding in deriving digital ASIC/FPGA requirements specification from higher-level (system or board-level) requirements specifications.Basic understanding upon concepts like RTL synthesis, Static Timing Analysis and correcting timing violations.Experience in Avionics protocols is a plus. Typical Education & Experience: Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry with 14 to 16 years of experience & Master's degree with 12+ years of experience. Relocation: This position offers relocation based on candidate eligibility Within INDIA.Export Control Requirements: Not an export control positionEqual Opportunity Employer:We are an equal opportunity employer. We do not accept unlawful discrimination in our recruitment or employment practices on any grounds including but not limited to; race, color, ethnicity, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military and veteran status, or other characteristics covered by applicable law.We have teams in more than 65 countries, and each person plays a role in helping us become one of the world's most innovative, diverse and inclusive companies. We are proud members of the Valuable 500 and welcome applications from candidates with disabilities. Applicants are encouraged to share with our recruitment team any accommodations required during the recruitment process. Accommodations may include but are not limited to: conducting interviews in accessible locations that accommodate mobility needs, encouraging candidates to bring and use any existing assistive technology such as screen readers and offering flexible interview formats such as virtual or phone interviews.Salary: . Date posted: 04/09/2024 03:52 PM

Senior Silicon Front-End Implementation Engineer

Microsoft Games, Multiple Locations, Any

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Senior Silicon Front End Implementation Engineer to work on leading edge IP development as part of the SCIPS Semi-custom and Central IP Silicon team. The candidate should be a motivated self-starter who will thrive in this cutting-edge technical environment. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. We're committed to a diverse and inclusive workplace and strongly encourage applicants from all background and walks of life . Difference makes us better.ResponsibilitiesYou will be a key link between front-end design and back-end teams. As a leader in the enablement of quality RTL and collateral file drops to PD, you will be responsible for implementing feedback and mitigations in the design constraints and toolchain to ensure best-case PPA. Strong communication skills will be needed to coordinate with RTL, DFT, CAD and physical design teams. You will participate in flow development, design automation, and correlation exercises to back-end flows. You are expected to work with limited direction and have attention to detail. You will also be expected to be able to provide crisp status of progress, issues, and risks on the program to the management team .Qualifications Required Bachelor of Science in Electrical or Computer Engineering 1 0 + years of experience in hardware design 8 + years of experience in Synthesis, Timing constraints, Front-end design checks and Power Performance Area (PPA) trade-offs Proficiency in collateral development including timing and synthesis constraints Proficiency in front-end design checks including LEC, Lint, Formal Equivalence, and CDC/RDC Proficiency in recent synthesis tool capabilities and methods for QoR improvement Proficiency in static timing analysis Familiarity with RTL and gate-level power analysis/optimization, UPF, and power-intent verification Experience with the project-level setup and configuration of 1 or more of the tools related to above disciplines Proficiency in translating physical design results into feedback for flow or RTL improvement Proficiency in Tcl , Perl, Python, shell programming Preferred Knowledge of full RTL2GDS flow Experience in ICC, power integrity analysis, ESD, PV Good communication and self- motivated that can collaborate with larger teams within Microsoft . Occasional travel Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form . Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.Salary: . Date posted: 04/18/2024 03:12 AM

Senior Engineer Logic Design

Microsoft Games, Multiple Locations, Any

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Senior Logic Design Engineer to work on leading edge IP development as part of the SCIPS Semi-custom and Central IP Silicon team. The candidate should be a motivated self-starter who will thrive in this cutting-edge technical environment. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. We're committed to a diverse and inclusive workplace and strongly encourage applicants from all background and walks of life . Difference makes us better.ResponsibilitiesYou will be responsible for all facets of design from working with architecture team, implementing the microarchitecture of IP blocks, RTL design, synthesis, static timing analysis, and silicon validation. Throughout the program you will be interacting with architects for feature definition, various design teams for leverage and collaboration, and software teams. Experience working with highspeed microarchitectures design required .Qualifications Required Bachelor of Science in Electrical or Computer Engineering 8 + years of experience in hardware design 2 + years of experience in Synthesis, Timing constraints, Power Performance Area (PPA) trade-offs 7 + years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINT closure. Worked with leading-edge technologies 5 nm or smaller . Experience in developing high speed CMOS designs . Proficient in System Verilog,C/C++, and scripting languagessuch as Python, Ruby or Perl Preferred Knowledge of the ARM architecture and experience with high-speed IO protocols such as PCI Express or USB Strong design knowledge of the industry standard bus interfaces such as AMBA AXI protocol Experienced in Basic floor planning, static timing analysis, closure and working with Physical design team. Experience with chip design quality through design and checklist reviews . Good communication and self- motivated that can collaborate with larger teams within Microsoft . Occasional travel #SCHIEINDIA Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form . Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.Salary: . Date posted: 04/18/2024 03:12 AM

Lead Product Engineer (Synthesis)

Siemens, Bangalore, Any

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design.Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs.The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime.This role is based in Bangalore. But you'll also get to visit other locations in India and globe, so you'll need to go where this job takes you. In return, you'll get the chance to work with teams impacting entire cities, countries, and the shape of things to come.This is your roleLead a Team of Engineers working on solving the latest design challenged in Logic SynthesisCollaborate with RnD and drive the roadmap for next generation RTL2GDSII solution.Work with design community in solving critical designs problems to achieve desired performance, area and power targets.Deployment of Synthesis solution with various customers working on cutting edge technologies (7nm and forward).Develop & deploy training and technical support to customers using Siemens EDA tools.We don't need superheroes, just superminds!Typically requires minimum of 8+ years of experience in Logic Synthesis flowsProficiency in Verilog, System Verilog & VHDL.Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design & implementation.Prior experience in IC digital design flows and front-end EDAT tools including Synthesis, DFT, Formal Verification, Logic Equivalence ChecksHands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must.Experience with advance technology nodes 7nm and below.Hands-on experience in debug & deliver solutions to critical design issues related to synthesis.TCL, Perl or Python scripting is a plus.Self-motivated team player with a zeal to drive high team performance.Good problem solving and debugging skills.Strong verbal & written communication skillsWe are SiemensA collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow!We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home.We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.#LI-EDA#LI-HybridSalary: . Date posted: 04/17/2024 09:19 PM

Silicon Front-End Implementation Engineer II

Microsoft Games, Bangalore, Any

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Silicon Front End Implementation Enginee r II to work on leading edge IP development as part of the SCIPS Semi-custom and Central IP Silicon team. The candidate should be a motivated self-starter who will thrive in this cutting-edge technical environment. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each da y we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. We're committed to a diverse and inclusive workplace and strongly encourage applicants from all background and walks of life . Difference makes us better.ResponsibilitiesYou will be a key link between front-end design and back-end teams. As a n enable r of quality RTL and collateral file drops to PD, you will be responsible for implementing feedback and mitigations in the design constraints and toolchain to ensure best-case PPA. Strong communication skills will be needed to coordinate with RTL, DFT, CAD and physical design teams. You will participate in flow development, design automation, and correlation exercises to back-end flows. You are expected to work with limited direction and have attention to detail. You will also be expected to be able to provide crisp status of progress, issues, and risks on the program to the management team.Qualifications Required Bachelor of Science in Electrical or Computer Engineering 5 + years of experience in hardware design 3 + years of experience in Synthesis, Timing constraints, Front-end design checks and Power Performance Area (PPA) trade-offs Proficiency in collateral development including timing and synthesis constraints Proficiency in front-end design checks including LEC, Lint, Formal Equivalence, and CDC/RDC Proficiency in recent synthesis tool capabilities and methods for QoR improvement Proficiency in static timing analysis Familiarity with RTL and gate-level power analysis/optimization, UPF, and power-intent verification Experience with the project-level setup and configuration of 1 or more of the tools related to above disciplines Proficiency in translating physical design results into feedback for flow or RTL improvement Proficiency in Tcl , Perl, Python, shell programming Preferred Knowledge of full RTL2GDS flow Experience in ICC, power integrity analysis, ESD, PV Good communication and self- motivated that can collaborate with larger teams within Microsoft . Occasional travel Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form . Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.Salary: . Date posted: 04/23/2024 03:19 AM

ASIC Engineer - Physical Design, OPD Hardware

Amazon, Bengaluru, KA, IN

DESCRIPTIONThe team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. As a Physical Design Engineer, you will:- Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure at the block and Sub System level.- Drive block physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off.- Work closely with third party design and fabrication services to deliver quality first pass silicon that meets all performance, power and area goals.- Drive and Develop Physical Design Tool features, Flow automations and Methodology enhancements in order to achieve PPA goals, low power requirements. - Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. TeamsWe are open to hiring candidates to work out of one of the following locations:Bangalore, KA, INDBASIC QUALIFICATIONS- BS in EE/CS- 5+ years of experience in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such as 5nm/7nm, 14/16nm- Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) to block design for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO- Scripting experience with Tcl, Perl or Python and ability to drive physical design flow automation.PREFERRED QUALIFICATIONS - MS or PhD degree in Computer Engineering/Electrical Engineering or related field - Excellent communication and analytical skills - Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO- 7+ years of experience in integrating IP and ability to specify and drive IP requirements in the physical domain- Thorough knowledge of device physics, custom/semi-custom implementation techniques- Experience solving physical design challenges across various technologies such as CPU, DDR, PCIe, fabrics etc.- Experience in extraction of design parameters, QOR metrics, and analyzing trends- Experience with DFT & DFM flows- Ability to provide mentorship, guidance to junior engineers and be a very effective team player