DESCRIPTIONThe team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. At Amazon, DFT (Design-for-Testability) is a multi-faceted job that involves architecture definition, logic design, verification, test patterns generation, chip bring-up and more. As a DFT Engineer, you will impact and see the device through its entire lifecycle, from definition stage to high volume production. You will be working in close collaboration with multiple VLSI engineering groups including design, verification, backend, test, reliability and more. As part of the chip design group, you will: - Contribute to the design and verification of DFT logic and components - Help to drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon - Review sign-off level timing closure using static timing analysis of DFT modes - Perform wafer probe testing, ATE testing, silicon bring-up, diagnosis and support for physical failure analysis - Take high volume chips to production with high coverage ATE test program We are open to hiring candidates to work out of one of the following locations:Bangalore, KA, INDBASIC QUALIFICATIONS - BS degree in Computer Engineering/Electrical Engineering - 5+ years in semiconductor companies as a DFT lead/manager - Chip design experience in Verilog and System Verilog - Chip verification experience, UVM methodology - Scan insertion tools and methodologies - MBIST and BISR, BIHR insertion tools and methodologies - EFUSE controllers and related structures - Top level DFT architecture definition experience - Gate-level simulations - Static timing analysis, DFT related timing closure - Scripting (Perl/Tcl) PREFERRED QUALIFICATIONS - MS or PhD degree in Computer Engineering/Electrical Engineering or related field - Excellent communication skills. Should be able to well communicate and establish relations with internal “customers”, - Manufacturing, and equipment vendors - Energetic, self-motivated - Pro-active, oriented on execution - Attentive to details and quality - Team player, with the ability to work in a rapidly evolving/changing environment - Ability to work well with overseas partners

Design Verification Engineer, Lab126

Amazon, Bengaluru, KA, IN

DESCRIPTIONAs a Design Verification (DV) Engineer, you will be part of an advanced architecture team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for advanced functional blocks. You will participate in the design verification and bring-up of such blocks by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team. You will participate in the lab bring-up of these blocks either in an FPGA or silicon by potentially writing test scripts, analyzing lab data, proposing experiments, etc.You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering, to architect and implement complex functional block that enable development of world-class hardware devices. In this role, you will:· Design world class hardware and software· Communicate and work with team members across multiple disciplines· Deliver detailed test plans for verification of complex digital design blocks by working with design engineers and architects· Create and enhance constrained-random verification environments using SystemVerilog and UVM· Identify and write all types of coverage measures for stimulus and corner-cases.· Debug tests with design engineers to deliver functionally correct design blocks.· Close coverage measures to identify verification holes and to show progress towards tape-out.· Participate in test plan and coverage reviewsThe ideal candidate should have experience with RTL development environments, fluency in modern hardware description languages and verification methodologies. They should have experience verifying complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. We are looking for a self-driven individual who can work with architects, HW and SW developers and can quickly resolve blocking issues.We are open to hiring candidates to work out of one of the following locations:Bangalore, KA, INDBASIC QUALIFICATIONSBachelor’s degree or higher in EE, CE, or CS 2+ years or more of practical semiconductor design verification including System Verilog, UVM, assertions and coverage driven verification. Experience developing UVM test bench, writing testplan, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality and performance with strong overall debug skills.Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python or Perl) for automationExcellent verbal and written communication skillsPREFERRED QUALIFICATIONSBS in Computer Science, Electrical Engineering, or related field. Experience with CPU block level testing Experience debugging system-level issuesStrong programming skills in C/C++ and scripting skills in Python and/or Perl Experience with high performance industry standard IO interfaces like AMBA AXI4, USB, MIPI etc.

Senior Engineer, Digital Verification

, chennai, IN

pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor's 30:year legacy of technology advancements and strong IP portfolio but with a new mission-to enhance Murata's world:class capabilities with high:performance semiconductors. With a strong foundation in RF integration, pSemi's product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi's team explores new ways to make electronics for the connected world smaller, thinner, faster and better.Job SummaryThis position is for a Senior Engineer, Digital Verification. The primary responsibilities include, but will not be limited to, technically guide test plan development, define the verification methodology and infrastructure, tracking deliverables to ensure timely execution with high quality.The Senior Engineer responsibilities will also include mentoring junior Verification Engineers.The individual will work closely with the digital design, and Product Development teams in India Design Center and global design centers. This position is located in pSemi India Design Center (IDC) in Chennai, India.Roles and ResponsibilitiesThis position has responsibility for::Development and deployment of verification and validation environment of digital circuits from scratch and (or) adapt and improve upon existing environment:Design, build, and maintain verification test suites to fully verify ICs:Deliver detailed test plans for verification of complex digital design blocks:Definition of verification simulation tool flow:Identify and write all types of coverage measures for stimulus and corner:cases:Debug tests with design engineers to deliver functionally correct design blocks:Close coverage measures to identify verification holes :Work with interdisciplinary teams to identify automation and tool requirements :Mentor junior verification engineers:Support independent product development and provide support for other design groups:Maintain a positive growth culture in IDCCompetency RequirementsIn order to perform the job successfully, an individual should demonstrate the following competencies: :Displaying Technical Expertise: Keeps his/her technical skills current; effectively applies specialized knowledge and skills to perform work tasks; understands and masters the technical skills, knowledge, and tasks associated with his/her job; shares technical expertise with others :Driving for Results: Aggressively pursues challenging goals and objectives; will to put in considerable time and effort to accomplish objectives; takes a highly focused, goal driven approach toward work :Making Accurate Judgments and Decisions: Bases decisions on a systematic review of relevant facts and information; avoids making assumptions or rushing to judgment; provides clear rationale for decisions:Working with Ambiguity: Achieves forward progress in the face of poorly defined situations and/or unclear goals; able to work effectively with limited or partial information:Critical Thinking: Skilled at finding logical flaws in arguments and plans; identifies problems and solutions that others might miss; provides detailed insight and constructive criticism into problems and complex situationsMinimum Qualifications (Experience and Skills):Typically requires 3 to 6 years of digital design verification experience, depending on education level:Proficiency in logic design verification:Ability to debug and perform root cause failure analysis at RTL and gate level:Demonstrated

Senior Staff Engineer, and Digital Verification Manager

, chennai, IN

pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor's 30:year legacy of technology advancements and strong IP portfolio but with a new mission-to enhance Murata's world:class capabilities with high:performance semiconductors. With a strong foundation in RF integration, pSemi's product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi's team explores new ways to make electronics for the connected world smaller, thinner, faster and better.Job SummaryThis position is for a Senior Staff Engineer, and Digital Verification Manager. The primary responsibilities include, but will not be limited to, managing in a hands:on fashion to technically guide test plan development, defining the verification methodology and infrastructure, tracking deliverables to ensure timely execution with high quality. As a technical leader/manager, this person is also responsible for leading/hiring engineers and building a strong design verification team. The individual will work closely with the digital design, verification, and Product Development teams in India Design Center and other design centers. This position is located in our India Design Center (IDC) in Chennai, India.Roles and ResponsibilitiesThis position has responsibility for::Development and deployment of verification and validation environment of digital circuits from scratch and (or) adapt and improve upon existing environment:Design, build, and maintain verification test suites to fully verify ICs:Deliver detailed test plans for verification of complex digital design blocks:Definition of verification simulation tool flow:Identify and write all types of coverage measures for stimulus and corner:cases:Debug tests with design engineers to deliver functionally correct design blocks.:Close coverage measures to identify verification holes :Work with interdisciplinary teams to identify automation and tool requirements :Manage Verification Team: Manage a team of verification engineers. Lead and maintain an efficient and technically proficient staff required to complete product development goals, manages team resources and schedules, and manages career development of team members, set staff's goals and conduct performance reviews, recruit and select candidates, provide orientation and training:Mentor verification engineers as needed:Support independent product development and provide support for other design groups:Maintain a positive growth culture in IDCCompetency RequirementsIn order to perform the job successfully, an individual should demonstrate the following competencies: :Displaying Technical Expertise: Keeps his/her technical skills current; effectively applies specialized knowledge and skills to perform work tasks; understands and masters the technical skills, knowledge, and tasks associated with his/her job; shares technical expertise with others :Driving for Results: Aggressively pursues challenging goals and objectives; will to put in considerable time and effort to accomplish objectives; takes a highly focused, goal driven approach toward work:Making Accurate Judgments and Decisions: Bases decisions on a systematic review of relevant facts and information; avoids making assumptions or rushing to judgment; provides clear rationale for decisions :Working with Ambiguity: Achieves forward progress in the face of inadequately defined situations and/or unclear goals; able to work effectively with limited or partial information:Critical Thinking: Skilled at finding logical flaw

Senior Staff Engineer, Digital Verification

, chennai, IN

pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor's 30:year legacy of technology advancements and strong IP portfolio but with a new mission-to enhance Murata's world:class capabilities with high:performance semiconductors. With a strong foundation in RF integration, pSemi's product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi's team explores new ways to make electronics for the connected world smaller, thinner, faster and better.Job Summary:This position is for a Sr. Staff Engineer who will join the IDC Chennai pSemi verification team. The primary responsibilities include but will not be limited to define the verification methodology and infrastructure, develop and deploy verification and validation environment of digital circuits, track deliverables to ensure timely execution with high quality. The individual will work closely with the digital design, verification, and Product Development teams in other design centers.Roles and ResponsibilitiesThis position has responsibility for::Development and deployment of verification and validation environment of digital circuits:Design, build, and maintain verification test suites to fully verify ICs:Deliver detailed test plans for verification of digital design blocks:Definition of verification simulation tool flow:Identify and write all types of coverage measures for stimulus and corner:cases:Debug tests with design engineers to deliver functionally correct design blocks.:Close coverage measures to identify verification holes :Run ATPG test vectors and verify scan chain:Work with interdisciplinary teams to identify automation and tool requirements :Work closely with the characterization and test teams to support post silicon validation:Technical and career growth of the team:Collaborate with cross functional teams in other geographical locations:Build strong relationships with design groups in other design centers:Support independent product development and provide support for other design groups:Collaborate with the IDC founding team and develop and maintain a positive growth culture in IDCCompetency RequirementsIn order to perform the job successfully, an individual should demonstrate the following competencies: :Working with Ambiguity: Achieves forward progress in the face of inadequately defined situations and/or unclear goals; able to work effectively with limited or partial information:Critical Thinking: Skilled at finding logical flaws in arguments and plans; identifies problems and solutions that others might miss; provides detailed insight and constructive criticism into problems and complex situations:Displaying Technical Expertise:Keeps his/her technical skills current; effectively applies specialized knowledge and skills to perform work tasks; understands and masters the technical skills, knowledge, and tasks associated with his/her job; shares technical expertise with others:Driving for Results:Aggressively pursues challenging goals and objectives; will to put in considerable time and effort to accomplish objectives; takes a highly focused, goal driven approach toward work:Making Accurate Judgments and Decisions:Bases decisions on a systematic review of relevant facts and information; avoids making assumptions or rushing to judgment; provides clear rationale for decisionsMinimum Qualifications (Experience and Skills):12+ years of experience in digital design and/or verification, depending on level of edu

Staff Engineer, Digital Verification

, chennai, IN

pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor's 30:year legacy of technology advancements and strong IP portfolio but with a new mission-to enhance Murata's world:class capabilities with high:performance semiconductors. With a strong foundation in RF integration, pSemi's product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi's team explores new ways to make electronics for the connected world smaller, thinner, faster and better.Job Summary:This position is for a Staff Engineer who will join the IDC Chennai pSemi verification team. The primary responsibilities include but will not be limited to define the verification methodology and infrastructure, develop and deploy verification and validation environment of digital circuits, track deliverables to ensure timely execution with high quality. The individual will work closely with the digital design, verification, and Product Development teams in other design centers.Roles and ResponsibilitiesThis position has responsibility for::Development and deployment of verification and validation environment of digital circuits:Design, build, and maintain verification test suites to fully verify ICs:Deliver detailed test plans for verification of digital design blocks:Definition of verification simulation tool flow:Identify and write all types of coverage measures for stimulus and corner:cases:Debug tests with design engineers to deliver functionally correct design blocks.:Close coverage measures to identify verification holes :Run ATPG test vectors and verify scan chain:Work with interdisciplinary teams to identify automation and tool requirements :Work closely with the characterization and test teams to support post silicon validation:Collaborate with cross functional teams in other geographical locations:Build strong relationships with design groups in other design centers:Support independent product development and provide support for other design groups:Collaborate with the IDC founding team and develop and maintain a positive growth culture in IDCCompetency RequirementsIn order to perform the job successfully, an individual should demonstrate the following competencies: :Working with Ambiguity: Achieves forward progress in the face of inadequately defined situations and/or unclear goals; able to work effectively with limited or partial information:Critical Thinking: Skilled at finding logical flaws in arguments and plans; identifies problems and solutions that others might miss; provides detailed insight and constructive criticism into problems and complex situations:Displaying Technical Expertise:Keeps his/her technical skills current; effectively applies specialized knowledge and skills to perform work tasks; understands and masters the technical skills, knowledge, and tasks associated with his/her job; shares technical expertise with others:Driving for Results:Aggressively pursues challenging goals and objectives; will to put in considerable time and effort to accomplish objectives; takes a highly focused, goal driven approach toward work:Making Accurate Judgments and Decisions:Bases decisions on a systematic review of relevant facts and information; avoids making assumptions or rushing to judgment; provides clear rationale for decisionsMinimum Qualifications (Experience and Skills):Typically requires 6 to 8 years of experience in digital design and/or verification, depending on level of education and experience:Profi

Design Verification Engineer, Lab126

Amazon, Bengaluru, KA, IN

DESCRIPTIONAs a Design Verification (DV) Engineer, you will be part of an advanced architecture team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for advanced functional blocks. You will participate in the design verification and bring-up of such blocks by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team. You will participate in the lab bring-up of these blocks either in an FPGA or silicon by potentially writing test scripts, analyzing lab data, proposing experiments, etc. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering, to architect and implement complex functional block that enable development of world-class hardware devices. In this role, you will: · Design world class hardware and software · Communicate and work with team members across multiple disciplines · Deliver detailed test plans for verification of complex digital design blocks by working with design engineers and architects · Create and enhance constrained-random verification environments using SystemVerilog and UVM · Identify and write all types of coverage measures for stimulus and corner-cases. · Debug tests with design engineers to deliver functionally correct design blocks. · Close coverage measures to identify verification holes and to show progress towards tape-out. · Participate in test plan and coverage reviews The ideal candidate should have experience with RTL development environments, fluency in modern hardware description languages and verification methodologies. They should have experience verifying complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. We are looking for a self-driven individual who can work with architects, HW and SW developers and can quickly resolve blocking issues. We are open to hiring candidates to work out of one of the following locations:Bangalore, KA, INDBASIC QUALIFICATIONSBachelor’s degree or higher in EE, CE, or CS7+ years or more of practical semiconductor design verification including System Verilog, UVM, assertions and coverage driven verification.Experience using multiple verification platforms: UVM test bench, emulator, software environments and system testingExperience defining verification methodologiesExperience with test plan development, test bench infrastructure, developing tests and verifying the designExperience with writing directed/constrained-random testsExperience identifying bugs in architecture, functionality and performance with strong overall debug skillsExperience verifying at multiple levels of logic from SoCs to full system testingExperience with industry standard tools and scripting languages (Python or Perl) for automationExcellent verbal and written communication skillsPREFERRED QUALIFICATIONSMS in Computer Science, Electrical Engineering, or related field.Experience with CPU block level testingExperience debugging system-level issuesStrong programming skills in C/C++ and scripting skills in Python and/or PerlExperience with high performance industry standard IO interfaces like AMBA AXI4, USB, MIPI etc.Experience with formal verificationExperience with embedded softwareExperience with transaction level modelingKnowledge of FPGA and emulation platformsKnowledge of SoC architecture

Signal Integrity Engineer, Amazon Devices

Amazon, Bengaluru, KA, IN

DESCRIPTIONAmazon Lab126 is an inventive research and development company that designs and engineers high-profile devices like the Kindle family of products. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc. Since then, we have worked to produce best-selling e-readers and tablets, as well as new inventions like Echo line of products, Fire TV and Fire phone. What will you help us create?Key job responsibilitiesAs a Signal Integrity Engineer, you will be part of Validation team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for Signal Integrity aspects, compliance, and interoperability of package substrate, PCB, Cable solutions and system-level SI for interfaces like PCIe, DDR, Clocks etc. You will also be responsible for contributing to package and platform design guideline development.You will work closely with multi-disciplinary groups including Board Design, System Architects, IP developers, and Design Engineering, to verify and deliver complex, high volume SoCs that enable development of world-class hardware devices. In this role, you will be:• Responsible for defining the design guidelines for internal and external design teams and delivering reference simulation docs for customers • Performing modeling of package substrate/PCB channels elements in 3D/2D EM simulation tools. • Working with silicon designers, platform designers, package designers, electrical validation teams, etc. to support interconnect and interface performance requirements. • Reviewing and evaluating package and board design and providing review feedback. • Responsible for providing power delivery solutions across platform, package and SOC level • Definition of worst-case currents and voltage drop scenarios, MIM/decoupling allocation, grid choices and analysis, droop control, SOC ESD compliance, On-die droop detectors, usage of on-die delivery solutions like VR, LDO, and Power gates. We are open to hiring candidates to work out of one of the following locations:Bangalore, KA, INDBASIC QUALIFICATIONS- Bachelors in Electrical or Computer Engineering/Computer Science - 4+ years in working on validation of ASIC/SoC products- High speed serial interface analog building blocks, protocol, specifications and test methods- Familiarity with Simulation tools (ADS, HFSS, PowerSI, PowerDC, Hyperlynx) to execute SI-PI simulations is required.- Experience with performing measurement, and correlating measurements to simulations.- Experience with modeling and simulation of high-speed interface interconnects/channel.- Excellent analytical and problem solving skillsPREFERRED QUALIFICATIONS- Masters in Electrical or Computer Engineering/Computer Science- Understanding of Power & signal integrity concepts such as differential impedance, jitter, insertion loss, return loss, termination, etc.- Scripting experience in any programming language (C++, Python, PERL, MATLAB) to develop automation scripts is a plus.- Experience in Analog IP Characterization (SerDes, PLL, DDR) is desirable.- Good understanding of High-Speed Analog/Digital Circuits, VLSI, semiconductor physics