Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Hardware, Infrastructure Management, and Fundamentals Engineering (HIFE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.ResponsibilitiesIn this high impact role on the team, you will be responsible to: Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification. Own complete PD execution of Sub-systems/Sub-chips instantiating/integrating multiple other Physical partitions. Own partition floorplanning for optimizing blocks for Power, Performance and Area. Collaborate and influence various aspects of PD Methodology will also be key. Have close collaboration with RTL team (RTL2PD liaison) to help drive and resolve design issues related to block closure. Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach. Implement robust clock distribution solutions using appropriate methods that meet design requirements. Make good independent technical trade-offs between power, area, and timing (PPA). Be able to guide and coordinate with all sub-partitions PD to be able to take the Sub-chip through PD (construction through signoff) closure. Additionally influence key pieces of PD implementation methodology or specific areas such as Clocking. Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues upfront and ensure those are fixed in the next PD TFM release from CAD or are updated in the design project layer (as appropriate). Mentor junior engineers on technical issues. Be fully hands-on in your individual ownerships as individual contributor and collaborate cross-team on aspects of SC/SS execution, integration & delivery. Qualifications BS/MS in Electrical or Computer Engineering Min 15+ years of experience in semiconductor design. Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams. Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification. Preferred: Large SoC/CPU/IP design tape-out experience in the latest foundry process nodes. Led PD teams to deliver multiple PD partitions integrated in a subchip/subsystem, having excellent project management skills and ability to juggle multiple projects at once. Strong understanding of constraints generation, STA, timing optimization, and timing closure. In-depth understanding of design tradeoffs for power, performance, and area. Hands on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs. Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, Fusion Compiler, Innovus etc. Experience and knowledge of formal equivalency checks, LEC, LP, UPF, reliability, SI, and Noise. Experience in driving/contributing/influencing PD Methodology will be required. Overall know how of PD-TFM, exposure and some hands-on experience with PD flows bring up/setup/flow flush and PD methodology will be a bonus. Strong problem-solving and data analysis skills. Automation skills using scripting languages such as Perl, TCL, or Python. Technically leading/guiding a team of multiple PD engineers in order to deliver a Sub-Chip/SoC will be a big plus. Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form . Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.Salary: . Date posted: 04/03/2024 03:17 AM

RTL Design Engineer

Siemens, Bangalore, Any

Hello Visionary!We know that the only way a business thrive is if our people are growing. That's why we always put our people first. Our global, diverse team would be happy to support you and challenge you to grow in new ways. Who knows where our shared journey will take you?Siemens founded the new business unit Siemens Advanta (formerly known as Siemens IoT Services) on April 1, 2019 with its headquarter in Munich, Germany. It has been crafted to unlock the digital future of its clients by offering end-to-end support on their outstanding digitalization journey. Siemens Advanta is a strategic advisor and a trusted implementation partner in digital transformation and industrial IoT with a global network of more than 8000 employees in 10 countries and 21 offices. Highly skilled and experienced specialists offer services which range from consulting to craft & prototyping to solution & implementation and operation - everything out of one hand.We are looking for Software Developer !You'll make a difference by:Being ad full FPGA development flow from logic design, place route, timing analysis closure.Developing RTL code to implement FPGA-based digital designs.Understanding the customer requirements and product definition and define architecture and detailed design spec.Micro-architecture and coding of assigned module in VHDL/VerilogProviding estimates on FPGA resources, computation bandwidth, and memory bandwidth.Implementation of the design for porting on FPGA after required optimization based on available resources and timing closure requirement.Integrating digital IP blocks from internal or external sources into the overall design, ensuring compatibility and functionality.Writing test bench for verifying design for complete scenario coverage.Conducting functional simulation and RTL-level verification using simulation tools (e.g., ModelSim) to verify the correctness of the RTL code and IP Blocks.Your success is grounded in:Holding a Bachelors B.Tech/Electrical and Electronics with proven record and good knowledge of implementing digital logic designs in FPGA systems to join our team in Bangalore. The successful candidate will have 3 to 5 years of relevant experience and will play a crucial role in the design and integration of RTL components for FPGA based complex projects. Strong RTL design experience in VHDL/VerilogProficient with digital logic design.Experience in IP design or SOC integrationExperience with advanced Xilinx/Intel FPGA families and the Xilinx/Intel development tools including Vivado/QuartusUnderstanding of ARM SoCs with AXI/AHB buses, peripherals, CPUs is desirable.Modeling the algorithms in Octave/MATLAB, generating test vectors, visualizing data.Working knowledge on interfacing with ADCs and DACs and interpreting their performance.Troubleshooting and debugging FPGA implementations on boards.Working knowledge of C/C++ is added advantage.Knowledge of Linux, Device Drivers and any scripting language such as TCL/Perl/python.Prior experience using industry standard tools for Lint, CDC etc. is desired.Experience with protocols like SPI, I2C, DDR, Ethernet, HDMI, PCIe etc.Highly motivated, self-starter with good interpersonal skills and a strong team playerExcellent communication, critical thinking, and problem-solving skillsYou would be working with a team of software and hardware developers collaborating globally with complete ownership of bringing up hardware, writing drivers and test firmware, and delivering prototypes.Join us and be yourself!We value your outstanding identity and perspective and are fully committed to providing equitable opportunities and building a workplace that reflects the diversity of society. Come bring your authentic self and build a better tomorrow with us. Protecting the environment, conserving our natural resources, encouraging the health and performance of our people as well as safeguarding their working conditions are core to our social and business dedication at Siemens.Make your mark in our exciting world at Siemens.This role is based in Bangalore and is an Individual contributor role. You might be required to visit other locations within India and outside. In return, you'll get the chance to work with teams impacting - and the shape of things to come.We're Siemens. A collection of over 379,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and imagination and help us shape tomorrow.Find out more about Siemens careers at: www.siemens.com/careersSalary: . Date posted: 04/02/2024 02:55 PM

Product Engineering Manager, DFT (Remote)

Siemens, Ottawa, Ontario, Canada

Siemens EDA is a global technology leader in electronic design automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics in order to deliver better products in the increasingly complex world of chip, board and system design.Position OverviewThe Tessent division seeks a highly motivated, creative, and energetic leader as Product Engineering Manager, specializing in design-for-test (DFT). Successful Product Engineering Managers possess strong leadership skills as well as deep technical knowledge.Tessent is the market and technology leader of automated tools for insertion of semiconductor design-for-test (DFT) structures, automatic test pattern generation (ATPG), embedded deterministic compression (EDT), memory built-in self-test (MBIST), logic built-in self-test (LBIST), diagnosis-driven yield analysis (DDYA), hierarchical DFT solutions such as Streaming Scan Network (SSN), and analog fault injection and test. This position presents a great opportunity for technical growth and exposure to state-of-the-art semiconductor designs while getting exposure to marketing and business.Responsibilities include but are not limited to: Product Engineering Managers have two main responsibilities: people management & execution of product engineering projectsManage a team of Product Engineers working on diverse DFT technologies and productsMotivate, inspire, and grow the technical knowledge and careers of Product EngineersBuild a team of subject-matter experts (SMEs) who are trusted advisors to customers and internal R&D teamsWork closely with Product Managers to align PE tasks and yearly goals with product objectives, strategies, and prioritiesSet the example as a subject-matter expert, demonstrating technology, debug, and tool use knowledgeExecute technical DFT and cross-functional projectsDefine and characterize new product capabilities needed to meet customer requirementsExpert user of Tessent products in field of expertiseWork collaboratively with Tessent R&D to prototype, evaluate, and test new DFT products and features within complex IC design flowsWork through complex technical issues and independently create solutions and new methodologiesLead beta programs and support beta partnersExplain complex principles in simple terms to broad audiencesCreate and deliver in-depth technical presentations, training material, white papers, contributed articles, and application notesDevelop and review tool documentation such as User and Reference manualsWork with customers as well as Siemens EDA stakeholders including regional application engineers, global support engineers, and marketingSome travel, domestic and internationalJob QualificationsThe successful candidate will possess the following combination of education and experience:BS degree in Electrical Engineering, Computer Science, Computer Engineering, or related field is required.Must have 8-10 years of experience, including 4+ years of experience in DFT for complex ASICs / SOCs in some of the following areas: Automatic test pattern generation (ATPG), internal scan, embedded scan compression (EDT), packetized test delivery (SSN), memory built-in self-test (MBIST), logic built-in self-test (LBIST), IEEE 1687 IJTAG, analog design and simulation, and hierarchical DFT implementation.Experience in managing and leading a team of engineers.Knowledge of IC design trends and emerging requirementsExposure to one or more adjacent IC disciplines such as the following a plus:RTL coding and verification using Verilog/SystemVerilog/VHDLSynthesis and timing analysisPlace and routeAdvanced IC packagingDFT and test for embedded IP coresFailure diagnosisATE use / test program developmentProficiency in a scripting language like TCL (preferred) or PythonExperience with Tessent products and flows is a plusSelf-motivated and results-oriented with strong problem-solving skillsExcellent organizational skillsExcellent written and verbal English language communication skillsProficiency in LINUX and Windows environmentsLocation can be remote, hybrid, or in-office at the following Tessent locations:Ottawa (Canada), Saskatoon (Canada)Why us?Working at Siemens Software means flexibility - Choosing between working at home and the office at other times is the norm here. We offer great benefits and rewards, as you'd expect from a world leader in industrial software.A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow!Siemens Software. Transform the EverydayCompensation is based on experience and market values. You will be asked what your expectations are. There are multiple perks beyond the basic health insurance package, including RRSP matching, share purchase matching, company paid diversity days, and an extensive employee assistance program.#LI-EDA#LI-HYBRID #LI -Remote#LI-AJ1Siemens is committed to creating a diverse environment and is proud to be an equal opportunity employer. Upon request, Siemens Canada will provide reasonable accommodation for disabilities to support participation of candidates in all aspects of the recruitment process. All qualified applicants will receive consideration for employment.By submitting personal information to Siemens Canada Limited or its affiliates, service providers and agents, you consent to our collection, use and disclosure of such information for the purposes described in our Privacy Notice available at www.siemens.ca.Siemens s'engage à créer un environnement diversifié et est fière d'être un employeur souscrivant au principe de l'égalité d'accès à l'emploi. Sur demande, Siemens Canada prendra des mesures d'accommodement raisonnables pour les personnes handicapées, dans le but de soutenir la participation des candidats dans tous les aspects du processus de recrutement. Tous les candidats qualifiés seront pris en considération pour ce poste.En transmettant des renseignements personnels à Siemens Canada limitée ou à ses sociétés affiliées, à ses fournisseurs de services ou à ses agents, vous nous autorisez à recueillir, à utiliser et à divulguer ces renseignements aux fins prévues dans notre Déclaration de protection de la confidentialité, que vous pouvez consulter au www.siemens.ca.Salary: . Date posted: 04/18/2024 02:01 PM

ASIC Engineer - Physical Design, OPD Hardware

Amazon, Bengaluru, KA, IN

DESCRIPTIONThe team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. As a Physical Design Engineer, you will:- Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure at the block and Sub System level.- Drive block physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off.- Work closely with third party design and fabrication services to deliver quality first pass silicon that meets all performance, power and area goals.- Drive and Develop Physical Design Tool features, Flow automations and Methodology enhancements in order to achieve PPA goals, low power requirements. - Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. TeamsWe are open to hiring candidates to work out of one of the following locations:Bangalore, KA, INDBASIC QUALIFICATIONS- BS in EE/CS- 5+ years of experience in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such as 5nm/7nm, 14/16nm- Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) to block design for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO- Scripting experience with Tcl, Perl or Python and ability to drive physical design flow automation.PREFERRED QUALIFICATIONS - MS or PhD degree in Computer Engineering/Electrical Engineering or related field - Excellent communication and analytical skills - Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO- 7+ years of experience in integrating IP and ability to specify and drive IP requirements in the physical domain- Thorough knowledge of device physics, custom/semi-custom implementation techniques- Experience solving physical design challenges across various technologies such as CPU, DDR, PCIe, fabrics etc.- Experience in extraction of design parameters, QOR metrics, and analyzing trends- Experience with DFT & DFM flows- Ability to provide mentorship, guidance to junior engineers and be a very effective team player