Enter position
Rtl Design Engineer Salary in Tamil Nadu - PayScale
Receive statistics information by mail
Unfortunately, there are no statistics for this request. Try changing your position or region.
Найдите подходящую статистику
Show more
Recommended vacancies
Senior Engineer, Digital Verification
, chennai, IN
pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor's 30:year legacy of technology advancements and strong IP portfolio but with a new mission-to enhance Murata's world:class capabilities with high:performance semiconductors. With a strong foundation in RF integration, pSemi's product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi's team explores new ways to make electronics for the connected world smaller, thinner, faster and better.Job SummaryThis position is for a Senior Engineer, Digital Verification. The primary responsibilities include, but will not be limited to, technically guide test plan development, define the verification methodology and infrastructure, tracking deliverables to ensure timely execution with high quality.The Senior Engineer responsibilities will also include mentoring junior Verification Engineers.The individual will work closely with the digital design, and Product Development teams in India Design Center and global design centers. This position is located in pSemi India Design Center (IDC) in Chennai, India.Roles and ResponsibilitiesThis position has responsibility for::Development and deployment of verification and validation environment of digital circuits from scratch and (or) adapt and improve upon existing environment:Design, build, and maintain verification test suites to fully verify ICs:Deliver detailed test plans for verification of complex digital design blocks:Definition of verification simulation tool flow:Identify and write all types of coverage measures for stimulus and corner:cases:Debug tests with design engineers to deliver functionally correct design blocks:Close coverage measures to identify verification holes :Work with interdisciplinary teams to identify automation and tool requirements :Mentor junior verification engineers:Support independent product development and provide support for other design groups:Maintain a positive growth culture in IDCCompetency RequirementsIn order to perform the job successfully, an individual should demonstrate the following competencies: :Displaying Technical Expertise: Keeps his/her technical skills current; effectively applies specialized knowledge and skills to perform work tasks; understands and masters the technical skills, knowledge, and tasks associated with his/her job; shares technical expertise with others :Driving for Results: Aggressively pursues challenging goals and objectives; will to put in considerable time and effort to accomplish objectives; takes a highly focused, goal driven approach toward work :Making Accurate Judgments and Decisions: Bases decisions on a systematic review of relevant facts and information; avoids making assumptions or rushing to judgment; provides clear rationale for decisions:Working with Ambiguity: Achieves forward progress in the face of poorly defined situations and/or unclear goals; able to work effectively with limited or partial information:Critical Thinking: Skilled at finding logical flaws in arguments and plans; identifies problems and solutions that others might miss; provides detailed insight and constructive criticism into problems and complex situationsMinimum Qualifications (Experience and Skills):Typically requires 3 to 6 years of digital design verification experience, depending on education level:Proficiency in logic design verification:Ability to debug and perform root cause failure analysis at RTL and gate level:Demonstrated